Verilog Hdl: A Guide To Digital Design And Systhesis (Record no. 133931)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00385nam a2200157Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 230913s9999 xx 000 0 und d |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.39 pla |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Planitkar, Samir |
| 245 #0 - TITLE STATEMENT | |
| Title | Verilog Hdl: A Guide To Digital Design And Systhesis |
| 250 ## - EDITION STATEMENT | |
| Edition statement | II |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | DELHI |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Name of publisher, distributor, etc. | PEARSON |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Date of publication, distribution, etc. | 2007 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 490 |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electronics Engineering |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Collection | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Total Checkouts | Full call number | Barcode | Date last seen | Bill date | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | Electronics and Communication Engineering | IPEC Library | IPEC Library | General Stacks | 16.10.2007 | BANSAL STATIONERS | 621.39 pla | 118284 | 13.09.2023 | 16.10.2007 | Reference |